Role: STA Physical Design Engineer
Location: Irvine, CA-Yes, Remote option available, BUT 2-3 weeks work in Irvine, CA is mandatory
Interview Process: Phone/Skype
Job Type: Contract
 

Senior STA Engineer We're looking for a highly skilled Senior Static Timing Analysis (STA) Engineer with deep expertise in Signal Integrity (SI), Power Integrity (PI), Design for Manufacturing (DFM), and chip finishing. The ideal candidate will have a strong background in physical design (PD), excellent project management skills, and the ability to lead and mentor junior engineers.
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Qualifications
• Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
• 5+ years of experience in STA closure for complex digital designs.
• Proven expertise in Signal Integrity (SI) and Power Integrity (PI) analysis, including understanding of crosstalk and IR drop effects.
• Solid knowledge of chip finishing methodologies, including timing sign-off and tape-out readiness checks.
• Familiarity with Design for Manufacturing (DFM) principles and their application in physical design.
• Experience with industry-standard EDA tools for STA (e.g., PrimeTime, Tempus).
• Strong understanding of physical design (PD) concepts, including floorplanning, placement, and routing.
• Excellent problem-solving, analytical, and debugging skills.
• Strong verbal and written communication skills with the ability to lead technical discussions and present complex information clearly.
• Experience with scripting languages (Tcl, Python, Perl) is a must.
• Experience with management skills like project planning, scheduling, and resource allocation is a plus.

Responsibilities
• Lead and execute STA closure for complex SoC designs, ensuring all timing constraints are met across multiple corners and modes.
• Perform comprehensive Signal Integrity (SI) and Power Integrity (PI) analysis to identify and resolve timing issues caused by signal coupling, IR drop, and ground bounce.
• Develop and implement chip finishing strategies, including ECO flows (Engineering Change Orders), to ensure designs are ready for tape-out.
• Drive Design for Manufacturing (DFM) initiatives by collaborating with the design and foundry teams to optimize the physical layout for manufacturability and yield.
• Work closely with the physical design (PD) team to provide guidance on timing-driven placement and routing.
• Develop and improve STA methodologies, scripts, and flows to increase efficiency and accuracy.
• Effectively communicate technical challenges, progress, and solutions to cross-functional teams and management.

• Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
• 5+ years of experience in STA closure for complex digital designs.
• Proven expertise in Signal Integrity (SI) and Power Integrity (PI) analysis, including understanding of crosstalk and IR drop effects.
• Solid knowledge of chip finishing methodologies, including timing sign-off and tape-out readiness checks.
• Familiarity with Design for Manufacturing (DFM) principles and their application in physical design.
• Experience with industry-standard EDA tools for STA (e.g., PrimeTime, Tempus).
 

All your information will be kept confidential according to EEO guidelines.