Role: Digital Design (RTL) Engineer

Location: Santa Clara, CA (Remote option available)

Job Type: Contract

Interview: Phone/Skype

We are seeking a seasoned Digital Design Engineer with 10+ years of experience in RTL design using Verilog/System Verilog, skilled in developing micro-architectural documentation, quality checks, and integration support for SoC designers. Preferred skills include Python scripting, low power design (UPF/CPF), and familiarity with Synopsys/Cadence tools.

#DigitalDesign #Verilog #RTLDesign #Synopsys #SystemVerilog #C2CHiring #remotejob

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