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In this position, the individual will be responsible for providing technical leadership in the defining full chip Memory BIST and DFT methodology. Responsibilities will include complete ownership of full chip MBIST and DFT implementation flow, development, delivery and debug of test patterns. Additional responsibilities include proactively working with EDA vendors to assess best in class tools / capability and benchmark them to drive compelling adoption arguments. He / She will also drive IP integration strategies that ensure quality ASICs and avoid schedule surprises. 

The individual will influence and shape Western Digital’s next generation Design-for-Test implementation capability to meet the demands of the ASIC design road map. The individual will provide technical coaching and mentoring to junior team members and ensure the continued growth and success of the team. Ability to work with minimal supervision and drive to exceed expectations is a plus. 

This position requires a Master’s Degree in Electrical Engineering or Computer Science with a minimum of 10 to 14 years of direct experience in Memory BIST / DFT with emphasis on full chip ownership. Proficiency in Synopsys and MentorGraphics Test flows experience in PERL/TCL/Shell scripting is a must. The individual must have proven hands on experience leading the tape out of multiple low power hierarchical and flat ASICs at 65nm/40nm/28 nm designs. Expertise in DFT Compiler, Tetramax and Tessent is a MUST. Experience with synthesis is a plus. Good verbal and written communication skills are required. 

Experience: 

5 - 8 years 

Must have: 

Experience in DFT architecture and implementation 

Experience in MBIST architecture and implementation 

Strong DFT/MBIST fundamentals 

DRC Clean up 

Coverage improvement 

Understanding and modifying MBIST algorithms 

Pattern validation flows 

Zero/Unit delay 

SDF based 

Diagnosis and Silicon Bring up flows 

Good to have: 

PERL/TCL Scripting 

Usage of assertions for monitoring clock frequencies and other test related registers 

Yield analysis and improvement flow 

Understand CLP constructs and can work in multi-voltage, multi-power design 

Expected Roles: 

Need to architect DFT based on the PETE, Design and Customer specifications 

Should be self motivated, self driven  and eager to learn 

BE/Btech//Mtech/ME

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