PhD Engineering Internship

  • Intern
  • Business Function: Engineering Support
  • Work Location: San Jose Great Oaks Headquarters--LOC_WDT_USCA23

Company Description

At Western Digital, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible.

At our core, Western Digital is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we’ve been doing just that. Our technology helped people put a man on the moon.

We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world’s biggest companies and public cloud, Western Digital is fueling a brighter, smarter future.

Binge-watch any shows, use social media or shop online lately? You’ll find Western Digital supporting the storage infrastructure behind many of these platforms. And, that flash memory card that captures and preserves your most precious moments? That’s us, too.

We offer an expansive portfolio of technologies, storage devices and platforms for business and consumers alike. Our data-centric solutions are comprised of the Western Digital®, G-Technology™, SanDisk® and WD® brands.

Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data.

Job Description

We are seeking highly motivated PhD candidates to apply their studies and contribute hands-on while working on our engineering teams during Summer 2022. Current PhD candidate whose focus is towards, but not limited to, Electrical Engineering, Computer Engineering, Mechanical Engineering, Materials Science & Engineering and graduating December 2022 and beyond are encouraged to apply.


We are recruiting for the following areas: 

  • Read/Write Channel Architecture Engineer - In this role, you will develop, simulate, and evaluate new architectural features and functions for a high technology digital signal processing chip that is used for recording and playback of digital information that resides on a Hard Disk Drive. Ideal candidates have a strong understanding of signal processing and information theory, as well as strong statistical analysis skills.
  • Device Engineering – In this role, you’ll focus on electrical characterization of flash memory chips with the goal of improving the Reliability & Performance of the memory cell. Day-to-day responsibilities include, performing electrical measurements of various aspect of memory cell reliability such as endurance, data retention, program/read disturb etc. and compare it across device from different process conditions following by statistical data analysis; working at root cause analysis of physical mechanism of cell reliability degradation and identifying their solutions that may comprise of optimizing electrical operation of memory cell; as well as improvement of cell fabrication process.
  • Wafer Fabrication & Process Engineering -  Wafer Fabrication & Process Engineers will assume responsibility in the area of semiconductor process engineering and work directly on new process modules, including materials research, and developing new process integrations schemes for 3D NAND memory technology. Primary job function will focus on utilizing thin film processing techniques such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition/Etching (ALD/ALE), Reactive Ion Etching (RIE), Rapid Thermal Processing (RTP) and Oxidation to fabricate semiconductor memory devices. Process development will also include Research & Development on unique processes and materials. Collecting structural analysis such as SEMs/TEMs and analyzing many forms of process data from experimental splits using statistical analysis software and conducting process optimization using design of experiments (DOE) will be required.
  • Firmware Engineering – These candidates will develop embedded servo firmware for hard disk drives in the areas of servo loop design, optimization, calibration & actuator, spindle-motor control, etc. Responsibilities include, designing and implement Servo Loop design for hard disk drives; creating servo firmware development plans and schedules to meet deadline and development specifications; driving process / team / program changes and Influences team’s outcomes; participating product development in Servo Loop design, integration and drive level failure analysis; and working independently and cross-functionally with the ASIC, Mechanical, Channel FW, and CTLR FW teams.  


What is the RAMP Program? The RAMP Program is supplemental to your day-to-day internship responsibilities. In this program, you will gain deeper exposure to Western Digital’s culture and the different parts of the organization. RAMP Program elements include:

  • Professional insights from leaders and professionals
  • Engaging networking activities with cohort
  • Equity, Inclusion & Diversity and Global Giving & Doing events


  • Current PhD candidate whose focus is towards, but not limited to, Electrical Engineering, Computer Engineering, Mechanical Engineering, Materials Science & Engineering and graduating December 2022 and beyond
  • Strong area of study in, but not limited to, electronics, nanofabrication, signal processing, optics, machine learning & artificial intelligence
  • Focus in in HDD, flash, semiconductor, components, nonvolatile memory industry 
  • Effective in problem solving and communication with cross-functional teams  
  • Exceptional written and verbal communication skills
  • Proficient in Microsoft Office applications 
  • 3 or more publications in area of study desired



Additional Information

All your information will be kept confidential according to EEO guidelines.