Senior Technologist, ASIC Development Engineering
- Bengaluru, Karnataka, India
- Business Function: ASIC Development Engineering
- Work Location: Bangalore PTP Office (IBP)--LOC_WDT_IBP
At Western Digital, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible.
At our core, Western Digital is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we’ve been doing just that. Our technology helped people put a man on the moon.
We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world’s biggest companies and public cloud, Western Digital is fueling a brighter, smarter future.
Binge-watch any shows, use social media or shop online lately? You’ll find Western Digital supporting the storage infrastructure behind many of these platforms. And, that flash memory card that captures and preserves your most precious moments? That’s us, too.
We offer an expansive portfolio of technologies, storage devices and platforms for business and consumers alike. Our data-centric solutions are comprised of the Western Digital®, G-Technology™, SanDisk® and WD® brands.
Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data.
Experience: 12+ Years
As a DFT expert you will be a part of the WD ASIC team and working on leading edge of data storage controllers. You will support ASIC flow from DFT architecture definitions, through implementation and verification till mass production test program and RMA failure analysis.
• Scan implementation at full chip /sub chip level using DFT compiler, ATPG.
• The individual will be responsible for full chip Synthesis environment for low power, high performance designs, development-debug of interface and core side constraints, clock tree analysis and assisting full chip timing convergence and timing closure.
• Additional responsibilities include proactively working with the DFT teams and EDA vendors to assess best in class tools / capability and benchmark them to drive compelling adoption arguments.
• The individual will also drive IP integration strategies that ensure quality ASICs and avoid schedule surprises
Work-Location : Bangalore
• B.E / B.Tech / M.E / M.Tech Degree.
• Experience in the DFT concepts.
• Experience in building and leading a team.
• Hands on experience on either DFT DRC and DFT insertion or ATPG pattern generation
• Experience in Pattern simulations – Zero delay and timing.
• Proficient in Synopsys memory BIST – SMS
• Proficient in Architecting, implementation and validation of Memory BIST
Western Digital thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.
Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.