Principal Engineer, ASIC Development Engineering
- Bangalore, India
- Business Function: ASIC Development Engineering
- Work Location: Bangalore SNDK Office--LOCATION-3-265
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5+ years of experience in full custom layout for Analog and mixed signal circuits
Should have hands-on experience in custom layout for analog and IO circuits (Bandgap, LDOs, Clocking circuits, GPIOs, DDR IOs, ESD circuits etc)
Familiarity with custom digital layout (i.e. high speed logic paths)
Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding)
Experience in layout delivery flow – different views generation like LIB, LEF, GDS, etc.
Strong experience in debugging DRC, ERC and LVS issues independently.
Aware of layout techniques to mitigate ESD, latch-up
Knowledge of design for reliability (i.e. EM, IR, self-heating, etc.)
Should have solid understanding of CMOS and FinFET process technologies and associated issues in deep sub-micron technologies i.e. 28nm, 16nm, 7nm
Also should have sound understanding of IC fabrication and reliability issues
Full familiarity with Cadence and Mentor Graphics layout tools
Experience in scripting in Perl and/or Skill to develop scripts for automation is an advantage
Should possess good documentation, communication and presentation skills
Experience of working in a multi-site environment
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