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The position is for 1 semiconductor memory circuit layout engineer to be involved with the development of test sites and product designs, resident with the design team.
The chosen candidate should have a minimum of 5-10 years of memory industry design experience.

Job Duty 1 - Full chip integration for memory chips and Array Diagnostic Monitors (ADM's)
Job Duty 2 - Full chip DRC and LVS verification
Job Duty 3 – Definition of full chip signal routing methodology
Job Duty 4 - Definition of full chip voltage grids and power distribution
Job Duty 5 - Establishing voltage/reference decoupling cap methodologies that work with signal, power, and fill requirements
Job Duty 6 – Defining floor plans of entire chips as well as subsystems

Required skills:
1) Expert layout of semiconductor logic, analogy, and hierarchical systems.
2) Mastery of industry standard physical design and layout tools such as Cadence and Virtuoso.
3) Ability to run design checking software, e.g. DRC, LVS.
4) Strong verbal and written communication skills.
5) Must be able to work in close, team oriented research environment.