Principal Engineer, ASIC Development Engineering (ASIC/FPGA Design Verification)
- Full-time
- Job Type (exemption status): Exempt position - Please see related compensation & benefits details below
- Business Function: ASIC Development Engineering
- Work Location: Bangalore Cosmos Office--LOC_WDT_Bangalore Cosmos Office
Company Description
Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.
Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.
Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.
Job Description
- BE/ME in ECE, Electronics, or equivalent
- 8-12 years of experience in RTL design verification for Block/IP/Sub-system/SOC
- Knowledge in synthesis and timing analysis
- Experience with FPGA verification - Advantage
- Experience & Knowledge with verilog and System Verilog for Verification , SVA, UVM - Strong Advantage
- Deep knowledge of the following tools is an advantage: cadence NCSim, simvision, vmanager, any simulator, and waveform debug EDA tools from mentor, Synopsys
- Knowledge simulation environment System Verilog - UVM based – advantage
- Developing testbench for constraint random environment, Metric driven verification
- Root-cause design issue and able explain in text form clearly with design knowledge.
- Experience in standard protocols such eMMC, UFS, USB, PCIe, and DDR4 – advantage
- Knowledge with Perl/python – advantage
- Problem-solving: Ability to break the problem into small parts and apply relevant techniques to drive required outcomes
- Good communication and/or interaction skills among groups - local and abroad
- Ability to communicate multiple interfaces inside the company
- innovation : able to use technology in new ways to create more efficient organization and improve alignment between technology initiatives and business goals.
- Familiar with version control systems such as Git
Qualifications
- BE/ME in ECE, Electronics, or equivalent
- 8-13 years of experience in RTL design verification for Block/IP/Sub-system/SOC
Additional Information
Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.
Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying