Senior Engineer, ASIC

  • 6221 S Racine Cir, Englewood, CO 80111, USA
  • Full-time

Company Description

Join SEAKR Engineering, a leading-edge provider of advanced electronics for space applications. Pushing the boundaries of technology on a mission to change the world for the better from space.

Job Description

Highly motivated ASIC RTL Design Engineer with extensive knowledge of digital circuit design, state machines, Boolean math and FPGAs.  Candidates should have the ability to work from requirements to develop a chiplevel specification and write the RTL to implement the design.  Candidates must have excellent verbal and written communication skills and be able to demonstrate strong analytical and problems solving skills.

SEAKR's focus is leading edge radiation hardened ASIC design for spaceflight.

The candidate must have experience with

  • Completing multiple FPGA or ASIC design using Verilog and/or VHDL of moderate to high complexity
  • Simulation and debug and have a working knowledge of synthesis operations and timing analysis
  • Scripting languages such as TCL and/or Python
  • Engage with other chip architects and at the SoC level to drive the
    architectural definition of the memory subsystem.
  • Collaborate 3rd party IP providers to evaluate against architectural goals and drive integration of IPs.
  • Partner with the physical design team to resolve implementation level details and tradeoffs.
  • Work closely with design-for-test, design verification, validation teams to test and ensure proper functionality.

 The preferred candidate shall have

  • ASIC/FPGA design experience including thorough design documentation, completion and review of RTL blocks, participation in code reviews, significant RTL debug, and working knowledge of CDC, reset and clock design 
  • Ability to solve digital lab debug problems with use of lab tools such as bench supplies, scopes and logic analyzers 
  • Knowledge of RTL design techniques for radiation upset mitigation and experience using multiple RTL languages are a plus.


Candidate shall also have leadership skills and ability to provide support and technical direction to junior engineers.  Clear written and verbal communication skills are required.

A Bachelor's degree in Electrical Engineering or Computer Science is desired.  Must have at least 15+ years of ASIC/FPGA experience.

Additional Information

  • SEAKR is an Equal Opportunity Employer - All your information will be kept confidential according to EEO guidelines. 
  • US Citizenship Required
  • SEAKR offers competitive compensation and excellent benefits.