Digital Logic Design Reuse Librarian

  • 6221 S Racine Cir, Englewood, CO 80111, USA
  • Full-time

Company Description

Join SEAKR Engineering, a leading-edge provider of advanced electronics for space applications. Pushing the boundaries of technology on a mission to change the world for the better from space.

Job Description

The Digital Logic Design Reuse Library (DRL) Librarian supports SEAKR’s FPGA, ASIC, DSP, and Verification groups with quality maintained reuse logic items and scripts.

DRL Librarian Essential Responsibilities:

  • Help make the decision on what fidelity level a candidate item should initially be placed in.
  • Review code in accordance with coding guidelines.
  • Enforce Subversion (SVN) repo/folder structure guidelines.
  • Help assess candidate item requests for inclusion in library and fidelity level.
  • Run candidate items through synthesis and place and route tools to check compatibility.
  • Run items in the DRL through new tool versions to identify tool limitations.
  • Track and communicate item bug fixes or updates for the user community.
  • Setup and maintain DRL item searchable index to communicate status of items and where they could be used.
  • Work in accordance with SEAKR process documents.

DRL Librarian Other Responsibilities:

  • Work with DRL item Subject Matter Expert (SME) to understand the function and fidelity of the item.
  • Work with the DRL Change Control Board to decide on the incorporation of bug fixes or functional upgrades to DRL items.
  • Work with DRL item SME to understand and communicate bug fixes.
  • Work with DRL item SME to understand and communicate functional upgrades.
  • Work with Third Party IP vendors to incorporate IP in DRL, correct any bugs, and target specific devices.
  • Review program logic designs, verification environments, and scripts for potential incorporation in the DRL.
  • Perform other duties as assigned.


  • A Bachelor's degree in Electrical Engineering or Computer Science is required.
  • 2+ years of experience in FPGA/ASIC development.
  • 2+ years of FPGA/ASIC design tool (simulation, synthesis, place & route) experience.
  • Experience with RTL simulation and debug.
  • Working knowledge of timing analysis.
  • Experience with Mentor Graphics Questasim, Sypglass(Lint/CDC), Synopsis Synplify Pro, Xilinx ISE and Vivado, and Actel/Microsemi Designer and Libero are a plus.
  • Experience with Subversion is a plus.
  • Experience with scripting languages (TCL, Python) is a plus.
  • Excellent verbal and written communication.
  • Ability to work on and stay organized with several tasks at once.
  • Ability to work well with many engineers across programs.
  • Knowledge of a variety of software systems including Word, E-mail, Excel and their application to SEAKR’s operations.

Additional Information

  • SEAKR is an Equal Opportunity Employer - All your information will be kept confidential according to EEO guidelines. 
  • US Citizenship Required
  • SEAKR offers competitive compensation and excellent benefits.  
  • Location: Colorado