Join SEAKR Engineering, a leading-edge provider of advanced electronics for space applications. Pushing the boundaries of technology on a mission to change the world for the better from space.

SEAKR is seeking a Verification Engineer who is responsible for construction and maintenance of simulation environments using System Verilog with UVM (Universal Verification Methodology).

• The candidate shall be able to construct a simple traffic agent and add it to an existing test environment. 
• Ability to construct sequences for an interface based on existing design documentation and requirements, without supervision, is required. 
• The candidate shall be able to add prediction and checking to an environment scoreboard at the direction of a more senior engineer. 
• Ability to construct entire UVM test environments and infrastructure is a plus. 
• The candidate shall be capable of diagnosing sophisticated test failures, filing results and be capable of analyzing code coverage to adjust agent sequence behavior. 
• Ability to analyze RTL (VHDL and Verilog) to diagnose test failures is a plus. 
• Ability to perform and evaluate regression tests for a design under test is a plus. 
• Ability to use simulation tools such as Mentor Graphics Modelsim/Questasim for verification and reporting is required. 
• Must be able to work effectively under pressure to meet tight deadlines.

A Bachelors degree in Electrical Engineering or Computer Science and at least 3 years of verification engineering experience are required.

• All your information will be kept confidential according to EEO guidelines. 
• US Citizenship Required
• SEAKR offers competitive compensation and excellent benefits.  
• Location: Colorado, Relocation available