Role: Design Verification Lead Engineer
Location: Austin, TX (Hybrid negotiable, no remote)
Type: Contract 
Interview: Phone/Skype
 

We're looking for a strong Lead DV Engineer with 10+ years in SoC verification across ARM ecosystems. Must be hands-on with C/SystemVerilog, UVM, PCIE/DDR, GLS, GIT, and experienced in debugging, team mentorship, and verification flows. Required tools: Synopsys/Cadence, SpyGlass, Simvision.

#DesignVerification #SystemVerilog #UVM #PCIE #DDR #ARMVerification #SpyGlass #Simvision #Python #Cadence #SOCVerification #C2CHiring

All your information will be kept confidential according to EEO guidelines.