Principal Engineer-ASIC Design (Integration)

  • Full-time

Company Description

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.

Job Description

Job Description

As a member of Microchip’s engineering community, your primary responsibility will be to the design, integration, and verification support of the Full Chip Architecture and Full Chip Control/Data busses for an advanced ASIC or FPGA. Microchip’s designs are an SOC with various Hard and Soft IP blocks that support many industry standard protocols.  

 

Duties & Responsibilities

General Full Chip Integration and Support

  • Detailed module design and integration, performance analysis and detailed design specification creation – a large component of this position is to work with all design teams to ensure seamless integration of all components on the device.
  • Detailed ownership of full chip documentation of the SOC or FPGA device and/or device family.
  • Participate in the Verilog implementation and integration of full chip capabilities including interface support, integration of full chip busses (control and data network-on-chip) and documentation support at the full chip level.
  • Support full chip post-layout timing closure and verification.
  • Participate in the investigation & assessment of legacy and emerging integration techniques and on-chip / off-chip network-on-chip (NOC) bus structures for both control and high-speed data paths.  Overall support of the full chip register map at the chip level is required.
  • Improve Data & Command processing bandwidth, reduce latencies & increase reliability.
  • Support porting the design into test chips and emulation platforms
  • Support pre-tapeout verification and post-tapeout validation/characterization of the system designed.
  • Work closely with FPGA support software and Firmware engineers to resolve hardware issues and customer issues.

Qualifications

Qualifications/Requirements

  • Experience is SOC IP development and Full Chip Integration
  • Strong technical leader that is also able to work in a team-oriented environment.
  • Strong Experience in Verilog design and design verification
  • Strong Experience in Static Timing Analysis and Verilog simulation tools
  • Ability to write detailed design specifications.
  • Good analytical, oral, and written communication skills.
  • Able to write clean, readable presentations.
  • Self-motivated, proactive team player.
  • Ability to work to schedule requirements.

Additional Information

Equal Opportunity Employer - Microchip is an Equal Opportunity/Affirmative Action Employer of Disabled/Veterans/Minorities/Women. We provide equal employment and affirmative action opportunities to applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability, or any other basis protected under applicable federal, state or local laws.

Applicants with Disabilities - If you need accommodation for any part of the employment process because of a medical condition or disability, please send us an email here with “Applicant Accommodation Request” in the subject line of the email. Alternatively, you may call us at 480-792-7330 to let us know the nature of your request.

For more information on applicable equal employment regulations, please refer to the EEO is the Law Poster and the EEO is the Law Poster Supplement. Please also refer to the Pay Transparency Policy Statement.