Sr. Design Engineer- III

  • 2200 Mission College Blvd, Santa Clara, CA 95054, USA
  • Contract

Company Description

Leading Semiconductor Industry 

Job Description

Description:

SR. Design Engineer

Skills required, not limited to the following
8+ Years of Experience
Experience in the following aspects of Front End Design
1. Knowledge of HDK and ACE environments a huge positive and advantage
2. RTL Coding
3. System Verilog and Verilog LRM specific knowledge
4. Handling of Packages, Structs and other complex data structures
5. EDA tool experience on RTL Compilation, Elaboration and Simulation
6. EDA Tool experience on the following tools
a. Synopsys VCS
b. Synopsys Spyglass Lint
c. Synopsys Spyglass CDC
d. Synopsys Spyglass DFT
e. Synopsys VCLP for low power
f. Synthesis using Design Compiler
g. Tessent ATPG generation
7. Timing Constraint Development and cleanup for a complex IP block
8. Developing DFT Insertion scripts
9. Perl coding for developing simple flows
10. UNIX Shell scripting for quick script development
Minimum Education: BSEE/CE minimum, (MS preferred)

Qualifications

Minimum Education: BSEE/CE minimum, (MS preferred)

Additional Information

All your information will be kept confidential according to EEO guidelines.