client of FiniteHR

• B. Tech. / M. Tech. with 5-8 years of experience in Synthesis, STA

• Expertise in synthesis of complex SoCs at block/top level and writing timing constraints for complex designs with multiple clocks and multiple voltage domains

• Expertise on post layout timing closure for multiple tape outs, including timing ECOs and STA signoff

• Expertise in I/O constraints developments for Industry standard protocols (e.g. DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Display etc...)

• Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm, 10nm

• Good knowledge of EDA tools from RC, DC, PT, PTSI

• Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints 

• Good knowledge of VLSI process and device characteristics

• Good understanding of deep submicron parasitic effects, crosstalk effects etc.

• TCL, perl scripting

B.Tech. /M.Tech.

5-8 years experience in Synthesis,STA

TCL,Perl Scripting

All your information will be kept confidential according to EEO guidelines.