Finite HR Consulting

Our Client SeviTech is looking for FPGA RTL Design Engineer / Senior Engineer

About our Client: http://sevitechsystems.com/

Job Designation: FPGA RTL Design Engineer / Senior Engineer

Job Location: Bangalore

Job Type: Permanent 

 FPGA RTL Design Engineer / Senior Engineer

Job Description:

• You will be responsible for IP / sub-system level micro-architecture development and RTL coding.

• Prepare block/sub-system level timing constraints.

• Integrate IP/sub-system.

• Perform basic verification either in IP Verification environment or FPGA.

Desired Skills and Experience:

• B. Tech. or M. Tech. with 8 to 10 years of experience.

• Experience in Logic design / micro-architecture / RTL coding is a must.

• Expertise in Verilog is a must.

• Should have knowledge of AMBA protocols - AXI, AHB, APB.

• Experience in Synthesis / Understanding of timing concepts in Xilinx FPGA Implementation is required. FPGA Proto-typing experience is a must.

• Experience in design of DDR / USB / PCIe controller or such complex protocols is a plus.

• Hands on experience in Multi Clock designs, Asynchronous interface are a must.

• Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc. is required.

• Knowledge of low power concepts and experience is a plus.

This is an Immediate Opportunity candidate with less than one month notice will be preferred.

M. Tech. / B. Tech.

This is an Immediate Opportunity; candidates with less than one month notice will be preferred. Please ignore this post if the above profile doesn’t match with your current Job Role.