·         Very strong DV engineer capable of working independently.

·         Must be able to build UVM agents, monitors, scoreboards from scratch.

·         Prior experience designing and implementing a verification environment for a complex RTL design (e.g. DMA controller, memory controller, CPU subsystem etc). 

·         Domain expertise in one or more of the following areas (AXI/AHB, PCIe, DDR, knowledge of ARM Cortex, Synopsys ARC, Cadence Tensilica, RISC-V embedded controllers etc)

Required Qualifications

·  BS degree in Electrical Engineering or Computer Science

·  Strong knowledge of SystemVerilog and working knowledge of recent verification methodologies (UVM)

·  Domain expertise in one or more of the following areas:

v  System-on-a-chip verification with multiple CPUs and fixed function units with AXI or NOC interconnects

v  Verification of embedded CPUs such as ARM, Tensilica, MIPS CPUs and interconnect subsystem through C/Assembly language tests

v  Verification of industry standard serial interfaces such as MIPI, USB, PCIe using industry standard VIP components

v  Ethernet Packet Processors, buffer managers, DMA engines etc

v  PHY layer verification of serial interfaces such as Ethernet, PCIe, USB etc.

·  Solid Linux environment skills including the use of Perl, Python or TCL to write/debug CAD tool scripts.

Preferred qualifications

·  Prior experience participating in the full life cycle of ASIC projects (architecture through silicon to production)

·  Prior experience setting up and debugging gate level simulations with SDF annotated timing.

·  Good communication skills, open and collaborative working style, team player