Hi,

Job Title: Design Verification Engineer (UVM)

Location: Sunnyvale, CA

Duration: Long Term contract

Mandatory Skill: Strong hands-on UVM expertise is a MUST.

Job Summary: We are looking for an experienced Design Verification Engineer with strong expertise in SystemVerilog and UVM (Universal Verification Methodology) to develop and execute verification environments for complex semiconductor designs. The ideal candidate should have hands-on experience in functional verification, testbench development, debugging, and coverage closure.

Key Responsibilities :

Develop and maintain reusable UVM-based verification environments.

Create and implement test plans, test scenarios, and verification strategies.

Develop constrained-random and directed test cases using SystemVerilog.

Build and maintain UVM components, including agents, drivers, monitors, sequencers, and scoreboards.

Develop assertions using SystemVerilog Assertions (SVA).

Perform functional, code, and assertion coverage analysis.

Debug simulation failures and identify design or testbench issues.

Work closely with RTL designers and architecture teams to understand design specifications.

Drive functional coverage closure and achieve verification sign-off.

Participate in design reviews, verification planning, and regression analysis.

Automate verification tasks using scripting languages such as Python, Perl, or Shell.

Required Skills

Strong hands-on experience in UVM-based functional verification.

Excellent knowledge of SystemVerilog.

Experience developing reusable UVM testbenches from scratch.

Strong understanding of OOP concepts and constrained-random verification.

Experience with UVM sequences, sequencers, drivers, monitors, agents, and scoreboards.

Hands-on experience with SystemVerilog Assertions (SVA).

Knowledge of functional coverage and code coverage.

Experience with simulation and debugging tools such as:

Synopsys VCS

Cadence Xcelium

Siemens Questa

Strong debugging and problem-solving skills.

Good understanding of digital design concepts and RTL verification methodologies.

All your information will be kept confidential according to EEO guidelines.