Introduction

Are you a digital electronics designer with experience in design and/or functional verification of complex digital ASICs? We are seeking to strengthen our capabilities in digital-on-top design and in functional verification of our ASICs and aim to share this expertise and best practices with collaborating groups in the broader high-energy physics community. Working in the 130nm, 65nm and 28nm CMOS technology nodes or below, we aim for first-time-right designs with high performance and robust behaviour in the harsh environment of the LHC experiments. Take part!

Functions

You will join the Electronic Systems for Experiments Group (ESE) of the Experimental Physics Department (EP), which designs electronic systems, including ASICs, for the experiments at CERN and also supplies a series of electronics related services. The Microelectronics section (ME) develops analogue and digital integrated circuits for the readout and control of the CERN experiments.

As an ASIC digital design and verification engineer in the Microelectronics section of the ESE group, you will:

• Participate in the design and/or verification of digital and mixed-signal ASICs for the LHC experiments as part of a team.
• Provide design and/or verification support to other ASIC designers in collaborating High-Energy Physics Institutes.
• Share knowledge, as an expert in design and/or verification of complex ASICs, with others both within the CERN group and with the broader high-energy physics community.

Master's degree or equivalent relevant experience in the field of electronics engineering or a related field.

Experience:

The experience required for this post is:

• Proven experience and knowledge of Cadence EDA physical implementation tools.
• Demonstrated experience in the development of synthesizable Verilog RTL code, physical implementation (RTL to GDS), dynamic power analysis, physical verification of complex mixed-signal ASICs.
• Experience in functional verification of complex ASICs using standard verification methodologies such as UVM/OVM.
• Experience in defining and implementing coverage models, analysing results, and achieving verification closure.

Experience in the following fields will be considered an asset:

• Experience in the use of low power design techniques.
• Experience in fault injection techniques for Single Event Upsets (SEUs) mitigation.
• Experience with digital power analysis tools.
• Experience in flow automation scripts using Tcl, shell scripts and Perl/Python.
• Experience in the use of design methodologies for the mitigation of radiation effects (SEE and TID) in digital CMOS circuits.
• Experience of ASIC test methodology such as scan insertion, memory BIST and test pattern generation.
• Experience with the use of CAE tools for mixed mode microelectronics design: analog simulation, compact layout, extraction and re-simulation.

Technical competencies:

• Knowledge and application of high-level description languages and tools.
• Design and simulation of digital electronic circuits.
• Design and simulation of digital microelectronic circuits.
• Knowledge of radiation effects on electronics and mitigation techniques.

Behavioural competencies:

• Working in teams: understanding when teamwork is required to achieve the best results; including others accordingly and sharing information.
• Achieving results: having a structured and organised approach towards work; being able to set priorities and plan tasks with results in mind.
• Demonstrating flexibility: adapting quickly and resourcefully to shifting priorities and requirements.
• Communicating effectively: checking to ensure that the message has been well understood; ensuring that information, procedures and decisions are appropriately documented.
• Learning and sharing knowledge: keeping up-to-date with developments in own field of expertise and readily absorbing new information; sharing knowledge and expertise freely and willingly with others; coaching others to ensure knowledge transfer.

Language skills:

• Spoken and written English, with the ability to draw-up technical specifications and scientific reports and to make oral presentations.
• The ability to understand and speak French in professional contexts would be an advantage.

Eligibility and closing date:

Diversity has been an integral part of CERN's mission since its foundation and is an established value of the Organization. Employing a diverse workforce is central to our success. We welcome applications from all Member States and Associate Member States.

This vacancy will be filled as soon as possible, and applications should normally reach us no later than 04.08.2022

Employment Conditions

Contract type: Limited duration contract (2 years). Subject to certain conditions, holders of limited-duration contracts may apply for an indefinite position.

These functions require:

• Work in Radiation Areas.
• Work during nights, Sundays and official holidays, when required by the needs of the Organization.
• Stand-by duty, when required by the needs of the Organization.

Job grade: 6-7

Job reference: EP-ESE-ME-2022-69-LD

Benchmark Job Title: Electronics Engineer