ASIC digital design and EDA support engineer (EP-ESE-ME-2020-97-LD)
- Geneva, Switzerland
Are you a digital electronics designer with experience in digital design implementation and in Electronic Design Automation (EDA) tools? We are seeking to strengthen our capabilities in digital-on-top ASIC design implementation and in the development of EDA design flows for which we provide support to collaborating groups in the broader high energy physics community. Working on the 65nm node or below, we aim for designs with high performance and robust behaviour in the harsh environment of the LHC experiments. Thorough design implementation and robust design flows are key to minimise the number of iterations required for complex designs. Take part!
You will join the Electronic Systems for Experiments Group (ESE) of the Experimental Physics Department (EP), which designs electronic systems, including ASICs, for the experiments at CERN and also supplies a series of electronics related services. The Microelectronics section (ME) develops analogue, digital and mixed-signal integrated circuits for the readout and control of the CERN experiments.
As an ASIC digital design and EDA support engineer in the Microelectronics section of the ESE group, you will:
- Participate in the design of digital and mixed-signal ASICs for the LHC experiments as part of a team.
- Define, develop and maintain digital-on-top physical implementation flows embedding radiation tolerant design techniques using state-of-the-art EDA software tools.
- Establish and maintain an efficient working relationship with EDA software tool providers, IP vendors and silicon foundries.
- Provide support to ASIC designers in collaborating High-Energy Physics Institutes for the effective use of the physical design tool flows and process design kits (PDKs).
Master's degree or PhD or equivalent relevant experience in the field of electronics engineering or a related field.
The experience required for this post is:
- Deep knowledge of and extensive experience with Cadence EDA physical implementation and verification tools.
- Demonstrated experience in the development of synthesizable Verilog RTL code, physical implementation (RTL to GDS), physical and functional verification of complex mixed-signal ASICs.
- Experience in the use of design methodologies for the mitigation of radiation effects (SEE and TID) in digital CMOS circuits.
- Experience in developing process design kits (PDKs) using Cadence EDA tools.
Experience in the following fields will also be valued:
- Experience in the use of low power design techniques in modern CMOS processes (65nm and below).
- Experience in EDA and PDK user support.
- Experience in building and maintaining websites (SharePoint, Drupal) for EDA collaborative support purposes.
- Experience in the use and configuration of Design Data and IP Management platforms.
- Knowledge and application of high-level description languages and tools.
- Design and simulation of digital microelectronic circuits.
- Testing and measurement of digital microelectronic circuits.
- Knowledge of radiation effects on electronics and mitigation techniques.
- Working in teams: understanding when teamwork is required to achieve the best results; including others accordingly and sharing information.
- Achieving results: having a structured and organised approach towards work; being able to set priorities and plan tasks with results in mind.
- Demonstrating flexibility: adapting quickly and resourcefully to shifting priorities and requirements; readily absorbing new techniques and working practices; proposing new or improved ways of working; being willing to work on different projects simultaneously.
- Communicating effectively: checking to ensure that the message has been well understood; ensuring that information, procedures and decisions are appropriately documented.
- Learning and sharing knowledge: keeping up-to-date with developments in own field of expertise and readily absorbing new information; sharing knowledge and expertise freely and willingly with others; coaching others to ensure knowledge transfer.
- English: spoken and written with the ability to draw up technical texts (C1).
- The ability to understand and speak French in professional contexts would be an advantage.
Eligibility and closing date:
Diversity has been an integral part of CERN's mission since its foundation and is an established value of the Organization. Employing a diverse workforce is central to our success. We welcome applications from all Member States and Associate Member States.
This vacancy will be filled as soon as possible, and applications should normally reach us no later than 23.08.2020
Contract type: Limited duration contract (5 years). Subject to certain conditions, holders of limited-duration contracts may apply for an indefinite position.
These functions require:
- Work during nights, Sundays and official holidays, when required by the needs of the Organization.
Job grade: 6-7
Job reference: EP-ESE-ME-2020-97-LD
Benchmark Job Title: Electronics Engineer
Please make sure you have all the documents needed to hand as you start your application, as once it is submitted, you will not be able to upload any documents or edit your application further