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Posting Title: Circuit and System Validation Engineer

Job Overview: The DDR PHY systems team is looking for PHY post silicon validation/test & characterization engineers to support post silicon DDR bringup effort. He or She will be responsible for DDR lab debug support across various projects, DDR driver/firmware (DSF) code development for training algorithms, configuring HW blocks as needed for DRAM interface and will work on the validation of different DRAMs with different MSMs. They will automate flows to enable streamlining of the whole DDR validation processes. Hands on debug and analysis skills are a must, as the successful candidate will be performing driver/controller debug/analysis. Familiarity with DDR/LPDDR memory standards is also highly desirable.

Preferred Qualifications: -1+ years of experience with C/C++ coding -1+ years of lab debug & DDR debug experience

Preferred Qualifications: -1+ years of experience with C/C++ coding -1+ years of lab debug & DDR debug experience

All your information will be kept confidential according to EEO guidelines.