Digital ASIC Designer

  • Palo Alto, CA or Guilford, CT, CA, CT, us
  • Full-time

Company Description

Butterfly Network has created and brought to market the Butterfly IQ – the first FDA-cleared, portable device that puts ultrasound technology on a semiconductor chip. Pairing ultrasound-on-a-chip with the cloud and AI, we are doing something never done before, and bringing ultrasound to new domains around the world.

Since inception, Butterfly has raised over $375 million.

As we scale our team, we are seeking the best and the brightest engineers, across both the software and hardware worlds.

Job Description

The role of the Digital ASIC Designer offers the opportunity to work within the heart of the product development team and founders and to own the core of what will set Butterfly Network apart. This individual will design, implement, and verify digital signal processing, high speed interface, and system-on-a-chip logic for a suite of next-generation products.

Qualifications

  • BS or MS in Electrical Engineering, Computer Engineering, or Computer Science.
  • 4+ years of ASIC (preferred) or FPGA design, verification, and implementation.
  • Expert in SystemVerilog for design.
  • Experience with EDA tools such as functional simulation, synthesis, test insertion, static timing analysis, place-and-route, and clock tree synthesis.
  • Experience with system-on-a-chip design, including embedded microprocessors (e.g., ARM, Tensilica, Nios, MIPS), on-chip memories, and bus architectures.
  • Comfortable working in a Linux environment and using version control (e.g., SVN, Git, or Mercurial).
  • Familiar with Python, TCL, make, or other common scripting languages.
  • Must be organized and self-motivated, able to turn abstract ideas into concrete designs.
  • Must be a team player who enjoys working in a highly collaborative environment.


Ideal experience:

  • System Verilog verification with UVM, including constrained random verification, functional coverage and assertions.
  • Selecting and integrating complex 3rd party IP cores, such as PCI Express, USB, DDR-SDRAM, or 10G Ethernet.
  • Advanced CMOS process technology 45 nm or smaller.
  • High speed I/O such as multi-gigabit SerDes or DDR-SDRAM.
  • Integration with analog IP such as ADCs and PLLs.
  • Low-power design practices.
  • Implementation of digital signal processing algorithms.
  • Numeric programming with NumPy or Matlab.
  • C/C++ on embedded processors running bare-metal, an RTOS, or Linux.

Additional Information

All your information will be kept confidential according to EEO guidelines. Visa support provided as appropriate.

Videos To Watch